In time to digital converters it is desired to have a good integral nonlinearity (INL). Gated multipath ring oscillators (GRO) exist which perform a first order shaping. This first order shaping is achieved by storing the error on the gate capacitance. The working principle of these gated ring oscillators and the shaping are shown in FIG. 9. Even though these techniques improve the integral nonlinearity of a digital to time converter, the gated ring oscillator technique is not suitable for deep sub-micron CMOS technologies (e.g., 28 nm, 14 nm) due to gate leakage.
In digital PLL applications, the average measuring time may be 1 ns in comparison to a clock period of 32 ns (26 MHz). Thus, the gated ring oscillator technique is not applicable in digital PLLs in deep sub-micron CMOS technologies for a TDC integral nonlinearity improvement. In digital PLLs today, the induced spurs and phase noise performance degradation due to an integral nonlinearity of a time to digital converter is tolerated and is compensated with a narrow bandwidth in PLL loop filters.
Hence, it is desired to provide a concept which enables an improvement of the integral nonlinearity of a time to digital converter or in general of ring oscillators.